1. Field of the Invention
The present invention relates to an MIS (Metal Insulator Semiconductor) type semiconductor device and a method for manufacturing the same and, more specifically, to an SOI (Silicon on Insulator) type MISFET and a method for manufacturing the same.
2. Description of the Related Art
An FET (Field Effect Transistor) having an MIS structure, i.e., an MISFET, which is employed in an LSI (Large Scale Integration) circuit, a VSLI (Very Large Scale Integration) circuit, and further a power device, a CCD (Charge Coupled Device), etc., has been steadily decreased in size. The decrease in size, however, causes some problems, especially, a lowering in threshold voltage Vth due to the short channel effect or the like.
If the channel length of the MISFET is reduced to be almost equal to the depletion layer width of source and drain regions, both a gate voltage in the longitudinal direction and a drain electric field in the lateral direction have an effect (two-dimensional effect) on the distribution of potentials in the device. Therefore, the hypothesis that the electric field in the longitudinal direction is considerably stronger than that in the lateral direction cannot be made, in other words, a gradual channel approximation is not achieved, with the result that the short channel effect is manifested.
If the channel length is decreased, the charge of the channel region is effected by the charge in the source and drain regions as well as by the charge in the gate region, in virtue of the two-dimensional effect described above. Consequently, an inversion layer is formed by less gate charges or lower gate voltage, and the threshold voltage Vth is decreased. FIG. 1 illustrates the expanse of a depletion layer of the MISFET when the short channel effect appears. In FIG. 1, Q.sub.G indicates the charge effected by the gate, Q.sub.S does the charge effected by the source, and Q.sub.D does the charge effected by the drain. FIG. 2 schematically shows a typical example of equipotential lines in the MISFET when the short channel effect occurs.
If the threshold voltage Vth of the MISFET is expressed by: EQU Vth=V.sub.FB +.phi.s+Q.sub.B /Cox
(V.sub.FB : flat band voltage, .phi.s: surface potential on the source, Q.sub.B : charge of the depletion layer when the short channel effect is ignored, and Cox: electrostatic capacitance of gate insulating film)
variation in a threshold voltage .DELTA.Vth, caused by the decrease in size, is given as follows: EQU .DELTA.Vth=.DELTA..phi.s+.DELTA.Q.sub.B /Cox.
.DELTA..phi.s denotes a decrease in surface potential due to DIBL (Drain Induced Barrier Lowering). The DIBL is a phenomenon in which a potential barrier in the source is changed by the drain voltage. The term .DELTA.Q.sub.B /Cox indicates a threshold voltage drop due to a reduction in charge of the gate due to the foregoing short channel effect, which is called charge sharing.
An MISFET having an SOI structure capable of realizing a complete separation between elements by forming a silicon thin film on an insulation substrate, has recently attracted attention and, in particular, a full depletion type thin-film SOI device is being widely studied as a deep submicron device whose channel length is set to 0.1 .mu.m.
The thin-film SOI device has three great advantages: an increase in mobility due to a relaxation of vertical electric field in a channel region, a reduction in electrostatic capacitance of source/drain region, and suppression of short channel effect. These advantages allow a considerably high-speed operation.
It is known that an SOI transistor formed on an insulation film has the advantages of reducing an amount of stray capacitance and not being affected by soft errors. It is reported that, by thinning an SOI layer, it is completed depleted, the mobility of electrons or holes is increased, the switching characteristic is improved, and a threshold voltage drop due to a decrease in channel length (short channel effect) is smaller than that in an MISFET formed in bulk (M. Yoshimi et al., IEICE Trans., Vol. E74, p. 337, 1991).
FIG. 3 is a cross-sectional view of a conventional SOI-type MISFET. In this MISFET, a silicon oxide film layer 2 as an insulation film is formed on a p-type semiconductor substrate 1. On the silicon oxide film 2, an n.sup.+ -type source region 3 and an n.sup.+ -type drain region 4 are provided with a channel region 5 interposed therebetween. A silicon oxide film 6 as an insulation film is formed on the channel region 5, and a gate electrode 7 is formed on the silicon oxide film 6.
FIG. 4 illustrates the potential distribution when the gate voltage V.sub.G and drain voltage V.sub.D of the conventional SOI-type MISFET are Vth and 0.05V, respectively. Referring to FIG. 4, a depletion layer extends to the semiconductor substrate, and the equipotential lines are formed convexly in a ridge shape. In the convex potential distribution, the threshold voltage Vth is lowered in accordance with a reduction in channel length.
In the conventional SOI-type MISFET, the short channel effect is less than that of the MISFET formed in bulk, but the threshold voltage Vth is lowered in accordance with a reduction in channel length. Furthermore, the foregoing DIBL occurs as an unignorable problem in designing a deep submicron device.
Further, the thin-film SOI device (SOI-type MISFET) has a problem in which a threshold voltage is difficult to set. To reduce the electrostatic capacitance of the source and drain regions and suppress the short channel effect, the electrostatic capacitance between the SOI layer and substrate has to decrease. Since, in the conventional device, a silicon oxide film is used for a buried insulation film, the insulation film need to be thickened in order to reduce the capacitance. If, however, the buried insulation film is thickened, the electrostatic capacitance between the channel region and substrate is also reduced, and the threshold voltage is lowered too much.